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19-2029; Rev 0; 5/01
10-Bit Bus LVDS Serializers
General Description
The MAX9205/MAX9207 serializers transform 10-bitwide parallel LVCMOS/LVTTL data into a serial highspeed bus low-voltage differential signaling (LVDS) data stream. The serializers typically pair with deserializers like the MAX9206*/MAX9208*, which receive the serial output and transform it back to 10-bit-wide parallel data. The MAX9205/MAX9207 transmit serial data at speeds up to 400Mbps and 660Mbps, respectively, over PC board traces or twisted-pair cables. Since the clock is recovered from the serial data stream, clock-to-data and data-to-data skew that would be present with a parallel bus are eliminated. The serializers require no external components and few control signals. The input data strobe edge is selected by TCLK_R/F. PWRDN is used to save power when the devices are not in use. Upon power-up, a synchronization mode is activated, which is controlled by two SYNC inputs, SYNC1 and SYNC2. The MAX9205 can lock to a 16MHz to 40MHz system clock, while the MAX9207 can lock to a 40MHz to 66MHz system clock. The serializer output is held in high impedance until the device is fully locked to the local system clock, or when the device is in powerdown mode. Both the devices operate from a single +3.3V supply, are specified for operation from -40C to +85C, and are available in 28-pin SSOP packages.
Features
o Standalone Serializer (vs. SERDES) Ideal for Unidirectional Links o Framing Bits for Deserializer Resync Allow Hot Insertion Without System Interruption o LVDS Serial Output Rated for Point-to-Point and Bus Applications o Wide Reference Clock Input Range 16MHz to 40MHz (MAX9205) 40MHz to 66MHz (MAX9207) o Low 140ps (pk-pk) Deterministic Jitter (MAX9207) o Low 34mA Supply Current (MAX9205) o 10-Bit Parallel LVCMOS/LVTTL Interface o Up to 660Mbps Payload Data Rate (MAX9207) o Programmable Active Edge on Input Latch o Pin-Compatible Upgrades to DS92LV1021 and DS92LV1023
MAX9205/MAX9207
Ordering Information
PART MAX9205EAI MAX9207EAI TEMP. RANGE -40C to +85C -40C to +85C PINPACKAGE 28 SSOP 28 SSOP REF CLOCK RANGE (MHz) 16 to 40 40 to 66
Applications
Cellular Phone Base Stations Add Drop Muxes Digital Cross-Connects DSLAMs Network Switches and Routers Backplane Interconnect
Pin Configuration and Functional Diagram appear at end of data sheet.
Typical Application Circuit
PARALLEL-TO-SERIAL OUT+ 100 OUTPC BOARD OR TWISTED PAIR EN PWRDN MAX9205 MAX9207 *FUTURE PRODUCT MAX9206* MAX9208* PLL IN+ 100 INSERIAL-TO-PARALLEL BUS LVDS OUTPUT LATCH INPUT LATCH
10 IN_ TCLK_R/F TCLK
10 OUT_
REFCLK TIMING AND CONTROL CLOCK RECOVERY EN LOCK RCLK RCLK_R/F
PLL SYNC 1 SYNC 2
TIMING AND CONTROL
*Future product-contact factory for availability. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
10-Bit Bus LVDS Serializers MAX9205/MAX9207
ABSOLUTE MAXIMUM RATINGS
VCC to GND ........................................................-0.3V to +4.0V IN_, SYNC1, SYNC2, EN, TCLK_R/F, TCLK, PWRDN to GND......................................-0.3V to (VCC + 0.3V) OUT+, OUT- to GND .............................................-0.3V to +4.0V Output Short-Circuit Duration.....................................Continuous Continuous Power Dissipation (TA = +70C) 28-Pin SSOP (derate 9.5mW/C above +70C) ..........762mW Storage Temperature Range .............................-65C to +150C Junction Temperature ......................................................+150C Operating Temperature Range ...........................-40C to +85C Lead Temperature (soldering, 10s) .................................+300C ESD Protection (Human Body Model, OUT+, OUT-) ...........8kV
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, RL = 27 1% or 50 1%, CL = 10pF, TA = -40C to +85C. Typical values are at VCC = +3.3V and TA = +25C, unless otherwise noted.) (Notes 1, 2, 3)
PARAMETER High-Level Input Voltage Low-Level Input Voltage SYMBOL VIH VIL VIN_ = 0 or VCC RL = 27 RL = 50 CONDITIONS MIN 2.0 GND -20 200 250 286 460 1 0.9 1.15 3 -13 -10 -10 23 34 32 45 TYP MAX VCC 0.8 +20 400 600 35 1.3 35 -15 +10 +10 35 45 50 60 8 mA mA UNITS V V A mV mV mV V mV mA A A
LVCMOS/LVTLL LOGIC INPUTS (IN0 TO IN9, EN, SYNC1, SYNC2, TCLK, TCLK_R/F, PWRDN)
Input Current IIN BUS LVDS OUTPUTS (OUT+, OUT-) Differential Output Voltage Change in VOD Between Complementary Output States Output Offset Voltage Change in VOS Between Complementary Output States Output Short-Circuit Current Output High-Impedance Current Power-Off Output Current POWER SUPPLY VOD VOD VOS VOS IOS IOZ IOX
Figure 1 Figure 1 Figure 1 Figure 1
OUT+ or OUT- = 0, IN0 to IN9 = PWRDN = EN = high PWRDN or EN = 0.8V, OUT+ or OUT- = 0 or VCC VCC = 0, OUT+ or OUT- = 0 or 3.6V 16MHz 40MHz 40MHz 66MHz
Supply Current
ICC
RL = 27 or 50 worst-case pattern (Figures 2, 4) PWRDN = low
MAX9205 MAX9207
Power-Down Supply Current
ICCX
2
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10-Bit Bus LVDS Serializers
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, RL = 27 1% or 50 1%, CL = 10pF, TA = -40C to +85C. Typical values are at VCC = +3.3V and TA = +25C, unless otherwise noted.) (Notes 2, 4)
PARAMETER SYMBOL CONDITIONS MAX9205 MAX9207 MAX9205 MAX9207 Figure 3 MIN 16 40 -200 25 15.15 40 3 TYP MAX 40 66 200 62.5 25 60 6 150 UNITS MHz MHz ppm ns % ns ps (RMS)
MAX9205/MAX9207
TRANSMIT CLOCK (TCLK) TIMING REQUIREMENTS TCLK Center Frequency TCLK Frequency Variation TCLK Period TCLK Duty Cycle TCLK Input Transition Time TCLK Input Jitter SWITCHING CHARACTERISTICS Low-to-High Transition Time High-to-Low Transition Time IN_ Setup to TCLK IN_ Hold from TCLK OUTPUT High State to HighImpedance Delay OUTPUT Low State to HighImpedance Delay OUTPUT High Impedance to High-State Delay OUTPUT High Impedance to Low-State Delay SYNC Pulse Width PLL Lock Time Bus LVDS Bit Width Serializer Delay tLHT tHLT tS tH tHZ tLZ tZH tZL tSPW tPL tBIT tSD Figure 8 tTCP / 6 Figure 7 Figure 4 Figure 4 Figure 5 Figure 5 Figures 6, 7 Figures 6, 7 Figures 6, 7 Figures 6, 7 6 x tTCP 2048 x tTCP tTCP / 12 (tTCP / 6) +5 2049 x tTCP RL = 27 RL = 50 RL = 27 RL = 50 150 150 150 150 1 3 4.5 4.5 4.5 4.5 10 10 10 10 300 350 300 350 400 500 400 500 ps ps ns ns ns ns ns ns ns ns ns ns fTCCF TCFV tTCP TCDC tCLKT tJIT
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3
10-Bit Bus LVDS Serializers MAX9205/MAX9207
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, RL = 27 1% or 50 1%, CL = 10pF, TA = -40C to +85C. Typical values are at VCC = +3.3V and TA = +25C, unless otherwise noted.) (Notes 2, 4)
PARAMETER SYMBOL MAX9205 Deterministic Jitter (Figure 9) tDJIT MAX9207 MAX9205 Random Jitter (Figure 10) tRJIT MAX9207 CONDITIONS 16MHz 40MHz 40MHz 66MHz 16MHz 40MHz 40MHz 66MHz MIN TYP MAX 200 140 140 140 13 9 9 6 ps (RMS) ps (pk-pk) UNITS
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground except VOD, VOD, and VOS. Note 2: CL includes scope probe and test jig capacitance. Note 3: Parameters 100% tested at TA = +25C. Limits over operating temperature range guaranteed by design and characterization. Note 4: AC parameters are guaranteed by design and characterization.
Typical Operating Characteristics
(VCC = +3.3V, RL = 27, CL = 10pF, TA = +25C, unless otherwise noted.) WORST-CASE PATTERN SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX9205 toc01
DETERMINISTIC JITTER vs. SUPPLY VOLTAGE
MAX9205 toc02
50
60 DETERMINISTIC JITTER (ps, pk-pk)
SUPPLY CURRENT (mA)
40
50
40
30
30
20
TCLK = 40MHz MAX9205
20 10
TCLK = 40MHz MAX9205
10 3.0 3.3 SUPPLY VOLTAGE (V) 3.6
3.0
3.3 SUPPLY VOLTAGE (V)
3.6
4
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10-Bit Bus LVDS Serializers
Pin Description
PIN NAME FUNCTION LVCMOS/LVTTL Logic Inputs. The two SYNC pins are ORed. When at least one of the two pins are asserted high for at least six cycles of TCLK, the serializer initiates a transmission of 1024 SYNC patterns. If held high after 1024 SYNC patterns have been transmitted, SYNC patterns continue to be sent until the SYNC pin is asserted low. Toggling a SYNC pin after six TCLK cycles high and before 1024 SYNC patterns have been transmitted does not affect the output of the 1024 SYNC patterns. LVCMOS/LVTTL Data Inputs. Data is loaded into a 10-bit latch by the selected TCLK edge. LVCMOS/LVTTL Logic Input. High selects a TCLK rising-edge data strobe. Low selects a TCLK falling-edge data strobe. LVCMOS/LVTTL Reference Clock Input. The MAX9205 accepts a 16MHz to 40MHz clock. The MAX9207 accepts a 40MHz to 66MHz clock. TCLK provides a frequency reference to the PLL and strobes parallel data into the input latch. Digital Circuit Ground. Connect to ground plane. Analog Circuit Power Supply (Includes PLL). Bypass AVCC to ground with a 0.1F capacitor and a 0.001F capacitor. Place the 0.001F capacitor closest to AVCC. Analog Circuit Ground. Connect to ground plane. LVCMOS/LVTTL Logic Input. High enables serial data output. Low puts the bus LVDS output into high impedance. Inverting Bus LVDS Differential Output Noninverting Bus LVDS Differential Output LVCMOS/LVTTL Logic Input. Low puts the device into power-down mode and the output into high impedance. Digital Circuit Power Supply. Bypass DVCC to ground with a 0.1F capacitor and a 0.001F capacitor. Place the 0.001F capacitor closest to DVCC.
MAX9205/MAX9207
1, 2
SYNC 1, SYNC 2
3-12 13
IN0-IN9 TCLK_R/F
14 15, 16 17, 26 18, 20, 23, 25 19 21 22 24 27, 28
TCLK DGND AVCC AGND EN OUTOUT+ PWRDN DVCC
Detailed Description
The MAX9205/MAX9207 are 10-bit serializers designed to transmit data over balanced media that may be a standard twisted-pair cable or PC board traces at 160Mbps to 660Mbps. The interface may be doubleterminated point-to-point or a heavily loaded multipoint bus. The characteristic impedance of the media and connected devices can range from 100 for a point-topoint interface to 54 for a heavily loaded multipoint bus. A double-terminated point-to-point interface uses a 100-termination resistor at each end of the interface, resulting in a load of 50. A heavily loaded multipoint bus requires a termination as low as 54 at each end of the bus, resulting in a termination load of 27. The serializer requires a deserializer such as the MAX9206/MAX9208 for a complete data transmission application.
A high-state start bit and a low-state stop bit, added internally, frame the 10-bit parallel input data and ensure a transition in the serial data stream. Therefore, 12 serial bits are transmitted for each 10-bit parallel input. The MAX9205 accepts a 16MHz to 40MHz reference clock, producing a serial data rate of 192Mbps (12 bits x 16MHz) to 480Mbps (12 bits x 40MHz). The MAX9207 accepts a 40MHz to 66MHz reference clock, producing 480Mbps to 792Mbps. However, since only 10 bits are from input data, the actual throughput is 10 times the TCLK frequency. To transmit data, the serializers sequence through three modes: initialization mode, synchronization mode, and data transmission mode.
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5
10-Bit Bus LVDS Serializers MAX9205/MAX9207
Initialization Mode
When V CC is applied, the outputs are held in high impedance and internal circuitry is disabled by on-chip power-on-reset circuitry. When VCC reaches 2.35V, the PLL starts to lock to a local reference clock (16MHz to 40MHz for MAX9205 and 40MHz to 66MHz for MAX9207). The reference clock, TCLK, is provided by the system. A serializer locks within 2049 cycles of TCLK. Once locked, a serializer is ready to send data or SYNC patterns depending on the levels of SYNC 1 and SYNC 2. data transmission, the data at IN0-9 are ignored and SYNC patterns are sent for at least 1024 TCLK cycles. A start bit high and a stop bit low frame the 10-bit data and function as the embedded clock edge in the serial data stream. The serial rate is the TCLK frequency times the data and appended bits. For example, if TCLK is 40MHz, the serial rate is 40 x 12 (10 + 2 bits) = 480Mbps. Since only 10 bits are from input data, the payload rate is 40 x 10 = 400Mbps.
Power-Down
Power-down mode is entered when the PWRDN pin is driven low. In power-down mode, the PLL of the serializer is stopped and the outputs (OUT+ and OUT-) are in high impedance, disabling drive current and also reducing supply current. When PWRDN is driven high, the serializer must reinitialize and resynchronize before data can be transferred.
Synchronization Mode
To rapidly synchronize with a deserializer, SYNC patterns can be sent. A SYNC pattern is six consecutive ones followed by six consecutive zeros repeating every TCLK period. When one or both SYNC inputs are asserted high for at least six cycles of TCLK, the serializer will initiate the transmission of 1024 SYNC patterns. The serializer will continue to send SYNC patterns if either of the SYNC input pins remains high. Toggling one SYNC input with the other SYNC input low before 1024 SYNC patterns are output does not interrupt the output of the 1024 SYNC patterns.
High-Impedance State
The serializer output pins (OUT+ and OUT-) are held in high impedance when VCC is first applied and while the PLL is locking to the local reference clock. Setting EN or PWRDN low puts the device in high impedance. After initialization, EN functions asynchronously. For example, the serializer output can be put into high impedance while SYNC patterns are being sent without affecting the internal timing of the SYNC pattern generation. However, if the serializer goes into high impedance, a deserializer loses PLL lock and needs to resynchronize before data transfer can resume.
Data Transmission Mode
After initialization, both SYNC input pins must be set low by users or through a control signal from the deserializer before data transmission begins. Provided that SYNC inputs are low, input data at IN0-9 are clocked into the serializer by the TCLK input. Setting TCLK_R/F high selects the rising edge of TCLK for data strobe and low selects the falling edge. If either of the SYNC inputs goes high for six TCLK cycles at any time during
Table 1. Input /Output Function Table
INPUTS EN H PWRDN H SYNC 1 SYNC 2 OUTPUTS OUT+, OUTSynchronization Mode. SYNC patterns of six 1s and six 0s are transmitted every TCLK cycle for at least 1024 TCLK cycles. Data at IN0-9 are ignored. Data Transmission Mode. IN0-9 and 2 frame bits are transmitted every TCLK cycle. Output in high-impedance. L X X X
When either or both SYNC 1 and SYNC 2 are held high for at least six TCLK cycles L X L X
H X
H L
X = Don't care
6
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10-Bit Bus LVDS Serializers
Applications Information
Power-Supply Bypassing
Bypass AV CC with high-frequency surface-mount ceramic 0.1F and 0.001F capacitors in parallel as close to the device as possible, with the smaller valued capacitor closest to AVCC. Bypass DVCC with high-frequency surface-mount ceramic 0.1F and 0.001F capacitors in parallel as close to the device as possible, with the smaller valued capacitor closest to DVCC. Avoid the use of unbalanced cables such as ribbon or simple coaxial cable. Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to canceling effects. Balanced cables tend to pick up noise as common mode, which is rejected by a differential receiver. Eliminate reflections and ensure that noise couples as common mode by running the differential traces close together. Reduce skew by matching the electrical length of the traces. Excessive skew can result in a degradation of magnetic field cancellation. The differential output signals should be routed close to each other to cancel their external magnetic field. Maintain a constant distance between the differential traces to avoid discontinuities in differential impedance. Avoid 90 turns and minimize the number of vias to further prevent impedance discontinuities.
MAX9205/MAX9207
Differential Traces and Termination
Output trace characteristics affect the performance of the MAX9205/MAX9207. Use controlled-impedance media and terminate at both ends of the transmission line in the media's characteristic impedance. Termination with a single resistor at the end of a pointto-point link typically provides acceptable performance. However, the MAX9205/MAX9207 output levels are specified for double-terminated point-to-point and multipoint applications. With a single 100 termination, the output swing is larger.
OUT+ VOD OUT-
RL 2 VOS RL 2
TCLK
ODD IN_ EVEN IN_
TCLK_R/F = LOW
Figure 1. Output Voltage Definitions
Figure 2. Worst-Case ICC Test Pattern
90% TCLK 10%
90% 10%
3V
0
tCLKT
tCLKT
Figure 3. Input Clock Transition Time Requirement
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7
10-Bit Bus LVDS Serializers MAX9205/MAX9207
10pF OUT+ 80% RL VDIFF OUT10pF tLHT VDIFF = (OUT+) - (OUT-) tHLT 20% 20% 80% VDIFF = 0
Figure 4. Output Load and Transition Times
tTCP
TCLK
1.5V
1.5V
1.5V
tS 1.5V
tH 1.5V
IN_
TIMING SHOWN FOR TCLK_R/F = LOW
Figure 5. Data Input Setup and Hold Times
PARASITIC PACKAGE AND TRACE CAPACITANCE
10pF OUT+
13.5 +1.1V
OUTEN 10pF
13.5
3V EN 0 tHZ VOH 50% OUT 50% 1.1V tLZ tZL 1.1V 50% VOL 50% tZH 1.5V 1.5V
Figure 6. High-Impedance Test Circuit and Timing 8 _______________________________________________________________________________________
10-Bit Bus LVDS Serializers MAX9205/MAX9207
PWRDN
2.0V
0.8V
tPL
tHZ OR tLZ
TCLK
1.5V
tZH OR tZL
OUT SYNC 1 = SYNC 2 = LOW EN = HIGH TCLK_R/F = HIGH
HIGH IMPEDANCE
ACTIVE
HIGH IMPEDANCE
Figure 7. PLL Lock Time and PWRDN High-Impedance Delays
IN
IN0 - IN9 SYMBOL N tSD
IN0 - IN9 SYMBOL N + 1
TCLK
1.5V
TIMING SHOWN FOR TCLK_R/F = HIGH START BIT OUT TCLK_ R/F = HIGH VDIFF = 0 VDIFF = (OUT+) - (OUT-) OUT0 - OUT9 SYMBOL N STOP BIT START BIT OUT0 - OUT9 SYMBOL N+1 STOP BIT
Figure 8. Serializer Delay
(OUT+) - (OUT-) WAVEFORM (OUT+) - (OUT-) WAVEFORM O DIFFERENTIAL O DIFFERENTIAL
tDJIT SUPERIMPOSED RANDOM DATA
tRJIT
tRJIT "CLOCK" PATTERN (1010...)
Figure 9. Definition of Deterministic Jitter (tDJIT)
Figure 10. Definition of Random Jitter (tRJIT)
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9
10-Bit Bus LVDS Serializers MAX9205/MAX9207
Topologies
The serializers can operate in a variety of topologies. Examples of double-terminated point-to-point, multidrop, point-to-point broadcast, and multipoint topologies are shown in Figures 11 through 14. Use 1% surface-mount termination resistors. A point-to-point connection terminated at each end in the characteristic impedance of the cable or PC board traces is shown in Figure 11. The total load seen by the serializer is 50. The double termination typically reduces reflections compared to a single 100 termination. A single 100 termination at the deserializer input is feasible and will make the differential signal swing larger. A serializer located at one end of a backplane bus driving multiple deserializers in a multidrop configuration is shown in Figure 12. A 54 resistor at the far end terminates the bus. This topology allows "broadcast" of data with a minimum of interconnect.
SERIALIZED DATA PARALLEL DATA IN 100 100 PARALLEL DATA OUT
MAX9205 MAX9207
MAX9206 MAX9208
Figure 11. Double-Terminated Point-to-Point
ASIC
ASIC
ASIC
ASIC
ASIC
MAX9205 MAX9207
MAX9206 MAX9208
MAX9206 MAX9208
MAX9206 MAX9208
MAX9206 MAX9208
54
Figure 12. Multidrop 10 ______________________________________________________________________________________
10-Bit Bus LVDS Serializers MAX9205/MAX9207
A point-to-point version of the multidrop bus is shown in Figure 13. The low-jitter MAX9150 10-port repeater is used to reproduce and transmit the serializer output over 10 double-terminated point-to-point links. Compared to the multidrop bus, more interconnect is traded for more robust hot-plug capability. The repeater eliminates nine serializers compared to 10 individual point-to-point serializer-to-deserializer connections. Since repeater jitter subtracts from the serializer-deserializer timing margin, a low-jitter repeater is essential in most high data rate applications. Multiple serializers and deserializers bused over a differential serial connection on a backplane are shown in Figure 14. The second serializer can be a backup to the primary serializer. The typical close spacing (1in or less) of cards on a backplane reduces the characteristic impedance by as much as half the initial, unloaded value. Termination resistors that match the loaded characteristic impedance are required at each end of the bus. The total loaded seen by the serializer is 27 in this case.
Board Layout
For bus LVDS applications, a four-layer PC board that provides separate power, ground, and input/output signals is recommended. Separate LVTTL/LVCMOS and bus LVDS signals from each other to prevent coupling into the bus LVDS lines.
ASIC
ASIC
ASIC
MAX9205 MAX9207
MAX9206 MAX9208
MAX9206 MAX9208
MAX9150 REPEATER
100
100
100
100
Figure 13. Point-to-Point Broadcast Using MAX9150 Repeater
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11
10-Bit Bus LVDS Serializers MAX9205/MAX9207
ASIC
ASIC
ASIC
ASIC
ASIC
MAX9205 MAX9207
MAX9205 MAX9207
MAX9206 MAX9208
MAX9206 MAX9208
MAX9206 MAX9208
54
54
Figure 14. Multipoint
Pin Configuration
TOP VIEW
Functional Diagram
2 3 4 5 6 7 8 9
SYNC2 IN0 IN1 IN2 IN3 IN4 IN5 IN6
DVCC 27 AVCC 26 IN_
PARALLEL-TO-SERIAL
1
SYNC1
DVCC 28 INPUT LATCH 10
OUT+ OUT-
MAX9205 MAX9207
AGND 25 PWRDN 24 AGND 23 OUT+ 22 OUT- 21 AGND 20 EN 19 AGND 18 AVCC 17 DGND 16 DGND 15 SYNC 1 SYNC 2 TCLK_R/F TCLK
PLL
TIMING AND CONTROL
EN PWRDN
10 IN7 11 IN8 12 IN9 13 TCLK_R/F 14 TCLK SSOP
MAX9205 MAX9207
Chip Information
TRANSISTOR COUNT: 3036 PROCESS: CMOS
12
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10-Bit Bus LVDS Serializers MAX9205/MAX9207
Package Information
SSOP.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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